Online information, tools and references to complement Esperan training classes. You may also be interested in the Esperan tutorial section - freely downloadable PDF's on current and emerging languages and technologies.
General
Accellera
Industry-based standards organisation driving the development and enhancement of EDA languages and techniques, such as SystemVerilog; VHDL200x; Open Verification Library. A valuable resource for up-to-date information on the latest language developments.
Deepchip
John Cooley's (in)famous general EDA information site. Great for the latest news; user reviews of EDA tools and reports from major industry conferences.
Demos on Demand
Chiefly a collection of online vendor tool demos, but also contains a useful tutorials section which includes, for example, most of the tutorials, sessions and panel discussions from the last Design Verification Conference.
Open Cores
Free open source IP cores and chip designs.
VHDL
Hamburg VHDL Archive
Great list of links, VHDL tools, free models, and standards documentation
VHDL Quickstart Lecture
A lecture on the basic concepts of VHDL, including a suggested design flow. Available in various formats..
See also the VHDL-to-html convertor in the Tools section
Verilog
Rajesh Bawankule's Verilog Centre
Resource centre for Verilog, including alternative FAQ, links, tools documemtation.
Project Veripage
Good online Verilog, SystemVerilog and PLI tutorials, together with book links and core models.
See also the Verilog-to-html convertor in the Tools section.
SystemC
SystemC Homepage
Home of the Open SystemC Initiative (OSCI), steering SystemC development. Includes language reference, technical papers and download area for the SystemC reference simulator (requires registration).
SystemC 2.1 Online Reference
Online reference manual for the SystemC2.1 beta 11 release, built using the excellent Doxygen documentation system (see Tools section).
TCL/TK
Scripting White Paper
Discusses the differences between scripting and system programming, and shows why scripting languages (like Tcl) are better than software programming languages (like C or Java) for gluing together tasks and applications.
Expect Home Page
Expect allows Tcl control of interactive command line programs like ftp, rlogin or telnet. This site contains the Expect release as well as examples, papers and links.
Tools
jGRASP
Free parsing and folding text editor with VHDL mode and Control Structure Diagram (CSD) intended to improve readability of source code.
Regex Coach
The Regex Coach is a great interactive application to help learn, create and debug Regular Expressions (Regex), used in many languages such as Perl and Tcl as well as being a key component of many UNIX utilities.
LFSR Testbench
Small application for creating Linear Feedback Shift Registers (LFSR's) up to 16 bits in length with automatic generation of HDL code. Xilinx have a great application note XAPP052 (PDF) describing the background and application of these very useful circuits.
GHDL - Free VHDL Linux Simulator
Free, open-source VHDL simulator for Linux released under the GNU license.
SymphonyEDA
Fully-featured, low cost VHDL tool suite, including simulator, Graphical User Interface, waveform viewer, project manager and language-sensitive editor. There is a free restricted version useful for learning VHDL.
BlueHDL Simulator
Download a free Student version of the Blue Pacific BlueHDL simulator for VHDL, Verilog and SystemC. Unfortunately this software is now only available for Windows95, 98 and NT.
Open Source HDL Tools
Listing of open-source tools from SourceForge.
Doxygen
Superb documentation system for C++, C, SystemC and other object-oriented languages. Creates an online, fully linked graphical represention of any source code automatically, making it a great tool for extracting the code structure of unknown or undocumented code. See it in action with the SystemC2.1 release.
VHDL to HTML Converter
VHDLDOC is a tool to generate automatically hyperlinked html-documentation of VHDL code. Not quite as sophisticated as the Verilog HTML convertor below, and with some strict coding conventions, but useful for exploring undocumented or unfamiliar code.
Verilog to HTML Converter
Cool Verilog documentation tool which turns Verilog code into HTML pages. Includes linked hierarchial references, color syntax highlighting, signal/object tracing and index of design objects.