| New UVM Class Released As an alternative to our hugely successful OVM training, Esperan now offer a UVM course using the Accellera UVM1.0EA (Early Adopter) release. As UVM1.0ea is effectively OVM2.1, then the new SystemVerilog Advanced Verification with UVM1.0ea class is currently interchangeable with the OVM class, i.e. an engineer could attend either course and after completion, have the knowledge to use both UVM or OVM. Posted on 31-8-2010 3:12 pm New SystemVerilog Assertions (SVA) class Esperan's SVA class is very popular, with it's emphasis on writing good assertions rather than simply teaching language syntax. Now, based on customer feedback, we've made it even better. The new release has added content in three main areas:- Reusability is key for assertions. We have enhanced our content to demonstrate different methods of writing reusable properties for scalable Assertion Based Verification IP (ABV IP). There are many common assertion problems which are extremely difficult to express using SVA syntax alone. We have a new section on auxiliary code to demonstrate how to address these problems and how to write properties that are more efficient, understandable and hence easier to debug using auxiliary code and SVA syntax together. Formal verification (FV) is fast becoming mainstream. We have enhanced our course to include a fuller description of it's benefits and methodology. Also the entire course content has been updated for consistency with FV, so even if you're not yet using the technology, you can be confident that the assertion techniques we teach you conform to FV best-practices. This is a key failing of many other SVA classes and online content. Posted on 31-8-2010 3:11 pm Successful training sessions at CDNLive! EMEA Esperan again ran highly successful hands-on training sessions at Cadence's CDNLive! EMEA. We delivered three introductory one hour sessions, giving attendees the opportunity to learn about SystemVerilog, OVM and Formal Verification. The first of these sessions will shortly available as an online tutorial. Posted on 31-8-2010 3:10 pm Advanced e Verification Training Esperan's entry-level courses for Specman and have been a huge success and enthusiastically adopted by many key Specman users. In response to repeated requests for similar, high-quality training for experienced developers, Esperan has developed the e Advanced Verification course. Created with exclusive access to the best Specman experts in the world, this course covers advanced topics in coverage; reuse; messaging and temporal expressions, as well as detailed information on the new Intelligen random number generator; macros and advanced sequences. Posted on 31-8-2010 3:09 pm |
Esperan is internationally recognised as a high quality provider of training in VHDL, SystemVerilog, SystemC, PSL, SVA, OVM, TLM and for courses covering design, verification,
and PCB methodologies.
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