"Good background on verification methodology and an excellent introduction to e"

"Great class ... can't wait to start writing my own environments"

What is Specman Elite?
Specman Elite® is a tool which allows automated and reusable verification environments to be created using the e language. e is an industry and IEEE standard language (IEEE1647) and is unique in that it allows Aspect Orientated Programming (AOP) and powerful constrained random stimulus generation. Specman Elite® is part of the Cadence Incisive Enterprise Specman Simulator®, but is also interfaced to other simulators.

In this course, you will learn how to effectively use a verification environment created with the e language for Specman Elite®.

The course is based on a coverage driven verification methodology, which is applicable for a broad range of designs. The course shows how to create a reusable, block-level verification environment and then how to instantiate, customize and write tests for this environment. The verification methodology taught by this class is compatible with the Universal Verification Methodology (UVM).

After completing this course, you will have gained a better understanding of verification methodologies and will be able to apply these methodologies to rapidly create an efficient Specman environment for thorough design verification.

After sompleting this class you will be able to:-

• Describe the differences between Coverage Driven Verification (CDV) and directed tests.
• Describe the difference between CDV and Metric Driven Verification.
• Create reusable verification components (UVCs) that comply with the UVM methodology.
• Control stimulus generation using sequences, virtual sequences, and the UVM sequence API.
• Write and debug regular methods and Time Consuming Methods (TCMs).
• Invoke, run, and rerun Specman and the IUS simulator in a time-efficient way.
• Define, collect, and analyze functional coverage information.
• Use scoreboarding and assertions to perform data checks.
• Implement the “end of test“ and reset methodology using the Test Phase Flow .

4 days.

Delegates must be experienced with an HDL (Verilog or VHDL) and have some familiarity with verification concepts. No prior knowledge of Specman or e is required.

This is the only course that covers the latest Specman Elite version. The course uniquely utilises direct and unrestricted access to the insight, knowledge, experience and support from the people who create Specman Elite.

The topics covered in this course include:

• The design verification process
• Object-oriented concepts and dynamic structures
• Automation of constraint-driven random stimulus generation and variation
• Fundamentals of the e language
• Introduction to e Reuse Methodology
• Constructing flexible and powerful stimulus sequences
• Functional coverage

Day 1

• Introduction to Metric-Driven Verification (MDV)
• e Language basics
• Stimulus creation
• Stimulus variation and extendability

Day 2

• HDL simulator interaction
• Functional coverage fundamentals
• Universal Verification Methodology (UVM-e)

Day 3

• Debugging with Specman
• Physical layer (BFMs and monitors)
• Creating stimulus with sequences
• Data checking and scoreboards

Day 4

• Creating and packaging a UVM Verification Component (UVC)
• Specman use models
• e temporal language
• Comprehensive Specman coverage